1. Field of the Invention
The present invention relates to techniques for improving computer system performance. More specifically, the present invention relates to the design of a leakage-tolerant dynamic wide-NOR circuit structure.
2. Related Art
Designers use many arrangements of CMOS circuitry on a microprocessor chip. One common arrangement is a dynamic circuit. Dynamic circuits are beneficial because they provide reduced input capacitance and low switching thresholds, which results in increased switching speed. Moreover, the use of dynamic circuits leads to simple, area-efficient circuit layouts, which saves space on a semiconductor die. Unfortunately, due to their unique operating parameters, using dynamic circuits involves considering design complexities not encountered when using other types of CMOS circuits.
At the heart of the dynamic circuit is a dynamic node. Coupled to the dynamic node is a group of pull-down transistors that are arranged to perform a logic function for the dynamic gate. This group of pull-down transistors is coupled to Vss through an “evaluate” transistor. In addition, a “precharge” transistor is coupled between the dynamic node and Vcc.
The dynamic circuit functions in two phases; a “precharge” phase and an “evaluate” phase. During the precharge phase, the evaluate transistor is disabled and the precharge transistor charges the dynamic node to Vcc. Next, in the evaluate phase, the precharge transistor is disabled and the evaluate transistor is enabled. If the proper combination of inputs to the pull-down transistors is active during the evaluate phase, the pull-down transistors discharge the dynamic node to Vss through the evaluate transistor. Alternatively, if the proper combination of inputs is not active, the dynamic node remains in the precharged state.
One problem for dynamic circuits is “leakage current.” Leakage current is current that flows under the gate of a transistor despite the fact that the transistor is not “turned on.” As transistor gates become progressively narrower with each generation of process improvement, leakage current increases. Consequently, on chips that use the latest generation of transistors, the leakage current in dynamic circuits with multiple parallel pull-down transistors is large enough to discharge the dynamic node during the evaluate phase, thereby causing a “false evaluation.”
One way to prevent leakage current from causing a false evaluation is to use a “keeper” circuit to sustain the precharged value on the dynamic node. To be effective, the keeper must be large enough to deliver the current necessary to counterbalance the effects of leakage current. Therefore, the keeper must increase in size as the leakage current increases. Consequently, a dynamic circuit that has a large leakage current, such as a dynamic circuit with multiple parallel pull-down transistors, the keeper must be very large. In such a circuit, when only a limited number of pull-down transistors is active during the evaluate phase, the very large keeper can overwhelm the pull-down transistors and prevent the proper discharge of the dynamic node.
To avoid dynamic circuits with very large keepers, designers have optimized the circuits to minimize leakage current. In dynamic circuits with multiple parallel pull-down transistors, designers have minimized the leakage current by decreasing the number of pull-down transistors coupled to the dynamic node. For example, memory array designs have been reduced from 512 pull-down transistors to 128 pull-down transistors. Unfortunately, with each reduction in the number of pull-down transistors, the circuit becomes less useful. As leakage current continues to increase, designers will have to continue reducing the number of pull-down transistors coupled to the dynamic node, further limiting the usefulness of these circuits.
Hence, what is needed is a dynamic circuit with multiple parallel pull-down transistors that is tolerant of leakage current.